1. Field of Invention
The present invention relates to a frequency multiplier, and more particularly to a frequency multiplier circuit which is simple in structure and easy to cascade and provides precise frequency multiplication and a system thereof.
2. Description of Related Arts
The frequency multiplier is a circuit which generates an output signal whose frequency is a multiple of the frequency of an input frequency, for accomplishing multiplying frequency signals. Generally, a working clock of a digital circuit requires the frequency multiplier to have a high precision and a low noise. The ratio of the input clock to the input clock is called the frequency multiplication times.
The conventional frequency multiplier usually has a structure of phase locked loop (PLL) to satisfy requirements of the high precision and the low noise, but the structure has defects of a big cost of chips and difficulty in designing. Thus it is necessary to provide a frequency multiplier which has a simple structure and a small area of chips and is easy to cascade.